Document Type

Conference Proceeding

Publisher

IEEE

Faculty

Computing, Health and Science

School

Engineering

RAS ID

6034

Comments

This article was originally published as: Lachowicz, S. W., & Pfleiderer, H. (2008). Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA. Proceedings of 4th IEEE International Symposium on Electronic Design, Test and Applications. DELTA 2008. (pp. 474-477). Hong Kong: Hong Kong University of Science and Technology. IEEE. Original article available here

© 2008 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Abstract

The paper presents a novel method of evaluating the square root function in FPGA. The method uses a linear approximation subsystem with a reduced size of a look-up table. The reduction in the size of the lookup table is twofold. Firstly, a simple linear approximation subsystem uses the lookup table only for the node points. Secondly, a concept of a variable step look-up table is introduced, where the node points are not uniformly spaced, but the spacing is determined by how close to the linear function the approximated function is. The proposed method of evaluating nonlinear function and specifically the square root function is practical for word lengths of up to 24 bits. The evaluation is performed in one clock cycle.

DOI

10.1109/DELTA.2008.119

Access Rights

free_to_read

 
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Link to publisher version (DOI)

10.1109/DELTA.2008.119