Document Type

Conference Proceeding

Publisher

IEEE

Faculty

Computing, Health and Science

School

Engineering and Mathematics

RAS ID

2287

Comments

This conference paper was originally published as: Bermak, A. , & Martinez, D. (2001). A compact multi-chip-module implementation of a multi-precision neural network classifier. Proceedings of 2001 IEEE International Symposium on Circuits and Systems . (pp. 249 - 252 vol. 2). Sydney, NSW. IEEE. Original article available here

Abstract

This paper describes a novel MCM digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7 μm technology

DOI

10.1109/ISCAS.2001.921294

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Link to publisher version (DOI)

10.1109/ISCAS.2001.921294