Date of Award
2008
Degree Type
Thesis
Degree Name
Master of Engineering Science
School
School Of Engineering
Faculty
Computing, Health And Science
First Advisor
A/Prof. Adam Osseiran
Abstract
In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied.
Recommended Citation
Tourabaly, Jamiil A., "A jittered-sampling correction technique for ADCs" (2008). Theses: Doctorates and Masters. Paper 27.
http://ro.ecu.edu.au/theses/27