Title

Flexible multiplier blocks for accelerated processing in a 3D softchip adaptive computing system

Document Type

Conference Proceeding

Faculty

Faculty of Computing, Health and Science

School

School of Engineering and Mathematics

RAS ID

3569

Comments

Pfaender, O., Lachowicz, S., & Pfleiderer, H. J. (2005). Flexible multiplier blocks for accelerated processing in a 3D softchip adaptive computing system. IFIP VLSI-SoC 2005 : IFIP WG 10.5 International Conference on Very Large Scale Integration System-on-Chip.

Abstract

The 3D-SoftChip Adaptive Computing System utilizes advanced wafer bonding techniques to vertically integrate two 2D chips. It manipulates configurable hardware arithmetic primitives to form a powerful soft-configurable and highly efficient processing system, providing high computation power and data throughput for today's telecommunication, photonic networking and content-rich multimedia applications. This paper first reviews the 3D-SoftChip architecture and then concentrates on the accelerating processing elements which feature a run-time reconfigurable multiplier with data exchange interfaces and a concatenation option to enable adaptable word-length computations. A flexible and low-overhead multiplier architecture suitable for enhancing the array of processing elements is presented. Finally, the interconnect requirements for full-flexibility multiplication is estimated, and a simple way of transferring a considerable amount of control circuitry from the intelligent configurable switch into the processing elements to reduce the switch complexity is proposed.

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