Title

3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems

Document Type

Journal Article

Publisher

Hindawi Publishing Corporation

Faculty

Computing, Health and Science

School

Engineering and Mathematics

RAS ID

4535

Comments

C., Rassau, A., Lachowicz, S., Lee, M. M. O., & Eshraghian, K. (2006). 3D-SoftChip: A novel architecture for next-generation adaptive computing systems. EURASIP Journal on applied signal processing, 2006, 72-72. Original available here

Abstract

This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D) vertically integrated adaptive computing system combining state-of-the-art processing and 3D interconnection technology. It comprises the vertical integration of two chips (a configurable array processor and an intelligent configurable switch) through an indium bump interconnection array (IBIA). The configurable array processor (CAP) is an array of heterogeneous processing elements (PEs), while the intelligent configurable switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer, along with a direct memory access (DMA) controller. This paper introduces the novel 3D-SoftChip architecture for real-time communication and multimedia signal processing as a next-generation computing system. The paper further describes the advanced HW/SW codesign and verification methodology, including high-level system modeling of the 3D-SoftChip using SystemC, being used to determine the optimum hardware specification in the early design stage.

 

Link to publisher version (DOI)

10.1155/ASP/2006/75032