Title

Low memory visual saliency architecture for data reduction in wireless sensor networks

Document Type

Journal Article

Faculty

Faculty of Computing, Health and Science

School

School of Engineering / Centre for Communications Engineering Research

RAS ID

14787

Comments

This article was originally published as: Ngau, C., Ang, L. K., & Seng, K. (2012). Low memory visual saliency architecture for data reduction in wireless sensor networks. IET Wireless Sensor Systems, 2(2), 115-127. Original article available here

Abstract

Traditionally, to reduce communication overheads because of bandwidth limitations in wireless sensor networks (WSNs), image compression techniques are used on high-resolution captures. Higher data reduction rates can be achieved by first removing redundant parts of the capture prior to the application of image compression. To locate these redundant parts, biologically plausible visual saliency processing is used to isolate parts that seemed important based on visual perception. Although visual saliency proves to be an effective method in providing a distinctive difference between important and unimportant regions, computational complexity and memory requirements often impair implementation. This study presents an implementation of a low-memory visual saliency architecture with reduced computation complexity for data reduction in WSNs through salient patch transmission. A custom softcore microprocessor-based hardware implementation on a field programmable gate array is then used to verify the architecture. Real-time processing demonstrated that data reductions of more than 50% are achievable for simple to medium scenes without the application of image compression techniques.

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