Date of Award
2008
Document Type
Thesis
Publisher
Edith Cowan University
Degree Name
Master of Engineering Science
School
School of Engineering
Faculty
Faculty of Computing, Health and Science
First Supervisor
Associate Professor Adam Osseiran
Abstract
In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied.
Recommended Citation
Tourabaly, J. A. (2008). A jittered-sampling correction technique for ADCs. Edith Cowan University. Retrieved from https://ro.ecu.edu.au/theses/27