Document Type
Conference Proceeding
Publisher
IEEE
Faculty
Faculty of Computing, Health and Science
School
School of Engineering
RAS ID
6034
Abstract
The paper presents a novel method of evaluating the square root function in FPGA. The method uses a linear approximation subsystem with a reduced size of a look-up table. The reduction in the size of the lookup table is twofold. Firstly, a simple linear approximation subsystem uses the lookup table only for the node points. Secondly, a concept of a variable step look-up table is introduced, where the node points are not uniformly spaced, but the spacing is determined by how close to the linear function the approximated function is. The proposed method of evaluating nonlinear function and specifically the square root function is practical for word lengths of up to 24 bits. The evaluation is performed in one clock cycle.
DOI
10.1109/DELTA.2008.119
Access Rights
free_to_read
Comments
This is an Author's Accepted Manuscript of: Lachowicz, S. W., & Pfleiderer, H. (2008). Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA. Proceedings of 4th IEEE International Symposium on Electronic Design, Test and Applications. DELTA 2008. (pp. 474-477). Hong Kong: Hong Kong University of Science and Technology. IEEE. Available here
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