Title

Compensation of a winner take all circuit

Document Type

Conference Proceeding

Publisher

IEEE Press

Faculty

Faculty of Computing, Health and Science

School

School of Engineering and Mathematics / Centre for Communications Engineering Research

RAS ID

1566

Comments

Originally published as: Kothapalli, G. (2003, December). Compensation of a winner take all circuit. In Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on (Vol. 1, pp. 352-355). IEEE. Original article available here

Abstract

The design and simulation results of a CMOS winner-take-all (WTA) circuit are presented. A 16-cell test circuit has been designed for intended implementation in an 0.18 /spl mu/m CMOS process. This paper describes the architecture and design issues related to a CMOS WTA circuit. Several design issues such as high resolution, high speed, low power consumption, compactness, and high input voltage range have been addressed. The proposed circuit has a compact configuration of complexity O(N) where N denotes input count. It seems to be very suitable, especially for charge-based applications where input vectors are generated by a set of charged capacitances.

DOI

10.1109/ICECS.2003.1302049

 
COinS
 

Link to publisher version (DOI)

10.1109/ICECS.2003.1302049