Title

Programmable multi-task on-chip processing for CMOS imagers

Document Type

Conference Proceeding

Publisher

IEEE Computer Society

Faculty

Faculty of Computing, Health and Science

School

School of Engineering and Mathematics

RAS ID

2115

Comments

Originally published as: Boussaid, F., Bermak, A., & Bouzerdoum, A. (2003, July). Programmable multi-task on-chip processing for CMOS imagers. In MEMS, NANO and Smart Systems, 2003. Proceedings. International Conference on (pp. 227-232). IEEE. Original article available here

Abstract

Programmable multi-task on-chip processing is proposed for improving the performance of CMOS imagers in terms of sensitivity adaptation and image processing capabilities. The current-mode fully analog on-chip processing only performs computations during the readout and analog-to-digital conversion phases, removing the need for any in-pixel or focal-plane processing circuitry. A VLSI implementation, in AMI 0.5 /spl mu/m CMOS process, results in significant silicon area savings as processing circuitry accounts for less than 20% of the imager prototype core area. Only three externally tunable parameters are required to fully define the processing task to be carried out by the 32/spl times/32 CMOS imager prototype, which performs sensitivity adaptation, edge detection or image enhancement on read-out.

DOI

10.1109/ICMENS.2003.1221997

 
COinS
 

Link to publisher version (DOI)

10.1109/ICMENS.2003.1221997