Shunting inhibition-based on-chip processing for CMOS imagers
Document Type
Conference Proceeding
Publisher
IEEE
Faculty
Faculty of Computing, Health and Science
School
School of Engineering and Mathematics
RAS ID
91
Abstract
Biologically inspired shunting inhibition-based processing is shown to improve significantly the performance of conventional CMOS imagers in terms of dynamic range, sensitivity adaptation but also to provide image processing capabilities such as edge detection and image enhancement. A CMOS imager architecture using current-mode pixels and computation on readout is proposed, which enables shunting inhibition-based processing to be integrated on-chip with the pixels. Fully programmable, the architecture is based on a simple set of externally-tunable parameters that define the imager transfer characteristic, dynamic range compression and sensitivity as well as the type of image processing task requested.
DOI
10.1109/ICONIP.2002.1202833
Comments
Boussaid, F., Bermak, A., & Bouzerdoum, A. (2002, November). Shunting inhibition-based on-chip processing for CMOS imagers. In Neural Information Processing, 2002. ICONIP'02. Proceedings of the 9th International Conference on (Vol. 3, pp. 1310-1314). IEEE. Available here