Date of Award

2008

Degree Type

Thesis

Degree Name

Master of Engineering Science

School

School of Engineering

Faculty

Faculty of Computing, Health and Science

First Advisor

Associate Professor Adam Osseiran

Abstract

In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied.

Share

 
COinS