Date of Award
Master of Engineering Science
School of Engineering
Faculty of Computing, Health and Science
Associate Professor Adam Osseiran
In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied.
Tourabaly, J. A. (2008). A jittered-sampling correction technique for ADCs. https://ro.ecu.edu.au/theses/27