3D-SoftChip: A novel 3D vertically integrated adaptive computing system
Document Type
Conference Proceeding
Publisher
Springer
Faculty
Faculty of Computing, Health and Science
School
School of Engineering and Mathematics
RAS ID
3562
Abstract
This paper introduces a novel 3-Dimensional (3D) vertically integrated adaptive computing system. This 3D-SoftChip is a combination of state-of-the-art processing and interconnection technology. It comprises the vertical integration of two chips (a Configurable Array Processor and an Intelligent Configurable Switch) through indium bump 3D interconnections. The Configurable Array Processor (CAP) is an array of heterogeneous processing elements (PEs) while the Intelligent Configurable Switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer along with a Direct Memory Access (DMA) controller. This paper introduces the 3D-Softchip architecture for real-time communication and multimedia signal processing as a next generation computing system and describes the HW/SW codesign and verification methodology using SystemC.
Access Rights
free_to_read
Comments
Kim, C., Rassau, A., Lachowicz, S., Nooshabadi, S., & Eshraghian, K. (2005, February). 3D-SoftChip: A novel 3D vertically integrated adaptive computing system. In 2005 Thirteenth ACM International Symposium on Field Programmable Gate Arrays (p. 71-86). Available here