Author Identifier (ORCID)
Abstract
Wafer and FPGA testing remains costly in semiconductor manufacturing. This paper studies random sampling, stratified sampling, and k-means sampling under a partial-measurement setting with Gaussian Process Regression (GPR), and introduces Short Distance Elimination (SDE), a spatial screening rule that spreads selected training points over the layout. Combining value-based sampling with SDE yields two hybrid methods: S-SDE, which applies SDE within stratified subsets, and K-SDE, which applies SDE within k-means clusters. A calibration-based protocol fixes the value-group labels and SDE thresholds before target-file prediction. The SDE thresholds are selected from (Formula presented.) configurations in (Formula presented.), excluding (Formula presented.), using local window statistics and RMSD-based calibration sweeps. Both wafer and FPGA calibration files support (Formula presented.), which is then fixed for all remaining experiments. Experiments on industrial wafer data and actual FPGA silicon data, repeated across four random seeds, show that K-SDE reduces RMSD by 15.84% for wafer data and 13.03% for FPGA data relative to k-means sampling, while S-SDE reduces RMSD by 16.26% and 8.63% relative to stratified sampling.
Keywords
FPGA testing, Gaussian Process Regression, k-means, short distance elimination, spatial sampling, wafer testing
Document Type
Journal Article
Date of Publication
6-1-2026
Article Number
53
Volume
7
Issue
3
Publication Title
Signals
Publisher
MDPI
School
School of Science
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Wang, W., Adib, K. S. A., Ahmed, F., & Mian, R. (2026). Optimizing FPGA and wafer test coverage with spatial sampling and machine learning: Analysis of local spatial consistency. Signals, 7(3). https://doi.org/10.3390/signals7030053