Author Identifier (ORCID)
Abstract
Hardware–software co-design is a balanced strategy for computationally intensive algorithms such as decimal computing. It can provide several Pareto points for the development of embedded systems in terms of hardware cost and performance. In this study, we propose an efficient and accurate evaluation framework for decimal computing. The framework was designed and developed for hardware–software co-design decimal arithmetic using the RISC-V ecosystem. New binary and decimal-oriented instructions supported by an accelerator were developed. The framework can perform cycle-accurate analysis for performance and assess hardware overhead for co-design-based decimal arithmetic. Unlike previous studies that focused primarily on implementing and evaluating individual co-design methods, the proposed framework enables exhaustive hardware–software partition analysis at the building-block level, facilitating systematic exploration of the design space. We also evaluated the decimal floating-point multiplication Pareto points and identified a new Pareto point for hardware–software co-design-based decimal multiplication (Method-A) through an analysis with the proposed framework.
Keywords
decimal floating-point arithmetic, decimal hardware accelerator, decimal multiplication, hardware–software co-design, RISC-V, rocket chip
Document Type
Journal Article
Date of Publication
8-1-2026
Article Number
75
E-ISSN
26246120
Volume
7
Issue
4
Publication Title
Signals
Publisher
MDPI
School
School of Science
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Mian, R., & Inoue, M. (2026). An open-source evaluation framework for RISC-V co-design-based decimal arithmetic. Signals, 7(4). https://doi.org/10.3390/signals7040075